Presently, the electronic equipments are indispensable from our daily life. Consumers increasingly demand more processing power, lower electrical power usage and cheaper devices. As the electronic industry strive to meet these demands, miniaturization, resulting in more complicated and denser configurations, extends the number of chips per wafer, the number of transistors per chip, and reduces power usage. As the electronic components are made lighter, smaller, more multifunctional, more powerful, more reliable and less expensive, a wafer level packaging (WLP) technology has been gaining in popularity. The WLP technology combines dies having different functionalities at a wafer level, and is widely applied in order to meet continuous demands toward the miniaturization and higher functions of the electronic components.
The WLP technology adopts several operations to form a structure that includes multiple layers of different materials stacking on a wafer. In contrast to a traditional packaging technology, the WLP technology is crafted in a greater scale and more complicated working environment. Some factors, such as the uniformity within the wafer is critical for each layer disposed on the wafer. An undesirable offset may lead to a malfunction of a to-be-singulated integrated circuit.
As the size of the wafer used in the WLP technology becomes greater, there are more challenges to the yield of the manufacturing. As such, improvements in the structure and method for a WLP continue to be sought.